The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a chemical-mechanical polishing (CMP) process utilized in semiconductor manufacturing.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. One approach that has been implemented is referred to as a gate last process or gate replacement process. In the gate last process, dummy poly gates are initially formed and may be followed by normal CMOS process flow until deposition of an interlayer dielectric (ILD). CMP is typically performed on the ILD layer to expose the dummy poly gates. The dummy poly gates may then be removed and replaced with true metal gates. However, it has been observed that the conventional CMP process suffers from gate height control and may cause defects to the underlying layers. This can lead to poor device performance and low wafer yield.